Morteza Gholipour

Morteza Gholipour

مرتضی قلی پور
Email:  m.gholipour[at]

Assistant Professor
Assistant Professor
School of Electrical and Computer Engineering
Babol University of Technology
47148-71167, Babol, Iran

Ph.D., Electronics Engineering, University of Tehran, Tehran, Iran, 2009-2014
M.Sc., Electronics Engineering, University of Tehran, Tehran, Iran, 2000-2003
B.Sc., Electrical Engineering, Ferdowsi University of Mashhad, Mashhad, Iran, 1996-2000

Research Interests
Nanoelectronic circuits design
Emerging devices modeling and simulation (GNRFETs and CNTFETs)
VLSI systems and architectures

Honors and Awards
Previous and Present Positions
Assistant Professor, Babol University of Technology, since 2014

Professional Membership
Reviewer of the following publications:
-IEEE Transactions on Very Large Scale Integration Systems
-IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
-Microelectronics Journal, Elsevier
-International Journal of Numerical Modelling: Electronic Networks, Devices and Fields

Teaching Experiences
Advanced VLSI Design
Architecture of Custom Digital Signal Processors

VLSI System Design
Digital Logic Circuits
Computer Architecture

Journal Papers:

[1] M. Gholipour, Y.-Y. Chen, A. Sangai, N. Masoumi, and D. Chen, “Analytical SPICE-Compatible Model of Schottky-Barrier-type GNRFETs with Performance Analysis,” IEEE TVLSI, in press, 2015.

[2] M. GholipourN. Masoumi, Y.-Y. Chen, D. Chen, and M. Pourfath, “Asymmetric Gate Schottky-Barrier Graphene Nanoribbon FETs for Low-Power Design,” IEEE Transactions on Electron Devices, vol. 61, no. 12, pp. 4000-4006, Dec. 2014.

[3] M. Gholipour and N. Masoumi, “Graphene Nanoribbon Crossbar Architecture for Low Power and Dense Circuit Implementations,” Microelectronics Journal, Volume 45, Issue 11, November 2014, pp. 1533–1541.

[4] M. Gholipour, and N. Masoumi, “Design investigation of nanoelectronic circuits using crossbar-based nanoarchitectures,” Microelectronics Journal, Volume 44, Issue 3, March 2013, Pages 190–200.

[5] M. Gholipour, and N. Masoumi, “Efficient Inclusive Analytical Model for Delay Estimation of Multi-Walled Carbon Nanotube Interconnects”, IET Circuits Devices Syst., July 2012, Volume 6, Issue 4, p.252–259.

[6] K. Shojaee, M. Gholipour, A. Afzali-Kusha and M. Nourani, “Comparative Study of Asynchronous Pipeline Design Methods”, IEICE Electron. Express, Vol. 3, No. 8, pp.163-171, (2006).

Conference papers:

[1] M. Gholipour, Y-Y. Chen, A. Sangai, and D. Chen, “Highly Accurate SPICE-Compatible Modeling for Single- and Double-Gate GNRFETs with Studies on Technology Scaling,” Proceedings of IEEE/ACM Design, Automation & Test in Europe (DATE), Dresden, Germany, March 2014.

[2]  Y.-Y. Chen, A. Sangai, M. Gholipour, D. Chen, “Graphene nano-ribbon field-effect transistors as future low-power devices,” Low Power Electronics and Design (ISLPED), 2013 IEEE International Symposium on, pp. 151-156, 4-6 Sept. 2013.

[3] Y.-Y. Chen, A. Sangai, M. Gholipour, and D. Chen, “Schottky-Barrier-Type Graphene Nano-Ribbon Field-Effect Transistors: A Study on Compact Modeling, Process Variation, and Circuit Performance,” 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pp. 82-88, Jul. 2013.

[4] M. Gholipour, N. Masoumi, and H. Sheikhassadi, “Analytical Method for Crosstalk Peak Voltage Estimation of MWCNT Interconnects,” 21th Iranian Conference on Electric Engineering, Mashhad, Iran, May 2013.

[5] M. Gholipour, and N. Masoumi, “Efficient Model for Delay Estimation of MWCNT Interconnects,”International Conference on Microelectronics (ICM 2011), Tunisia, pp. 1-4, Dec. 2011.

[6] M. Gholipour, and N Masoumi, “A Comparative Study of Nanowire Crossbar and MOSFET Logic Implementations,” EUROCON-IEEE International Conference on Computer as a Tool, Lisbon, Portugal, pp. 1-4, 2011.

[7] M. Gholipour, H. Ahmadi Noubari, and M. Kamarei “A DSP Implementation of Lifting Based DWT for Image Processing Applications,” IEEE ICSIP Int. Conf., Dec. 2010, Changsha, China.

[8] M. Gholipour, and H. Ahmadi Noubari, “Hardware Implementation of Lifting Based Wavelet Transform,”IEEE ICSPS Int. Conf., Jul. 2010, Dalian, China, vol. 1, pp. 215-219.

[9] M. Gholipour, M. Nourani, D. Edwards, and A. Afzali-Kusha, "LLA: A Low Latency Asynchronous Control with applications," IEEE ISSCS Int. Conf., Jul. 2009, IasiRomania, pp. 513-516.

[10] M. Gholipour, A. Afzali-Kusha, and M. Nourani, "A Novel Low Latency Asynchronous Pipeline Control Circuit," Applied Electronics Int. Conf., Sep. 2008, Pilsen, Czech Republic, pp. 53-55.

[11] M. Gholipour, K. Shojaee, A. Afzali-Kusha, A. Khademzadeh and M. Nourani, "An Efficient Model for Performance Analysis of Asynchronous Pipeline Design Methods," IEEE ISCAS Conf., May 2005, Kobe,Japan, pp. 5234-5237.

[12] M. Gholipour, K. Shojaee, A. Khademzadeh, A. Afzali-Kusha and M. Nourani," Performance and Power Analysis of Asynchronous Pipeline Design Methods," 16th IEEE ICM Conf., December 2004, TunisTunisia, pp. 409-412.

[13] M. Gholipour, A. Afzali-Kusha, M. Nourani and A. Khademzadeh, "An Efficient Asynchronous Pipeline FIFO for Low-Power Applications," 45th IEEE MWSCAS Conf., August 2002, TulsaOklahoma, Vol. 2 pp. 481-484.

Supervised Dissertations and Theses
Research Projects
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