Mojtaba Valinataj

Mojtaba Valinataj

مجتبی ولی نتاج
Email:  m.valinataj[at]

Assistant Professor

Contact Information:

School of Electrical and Computer Engineering

Babol Noshirvani University of Technology

BabolIRAN - Postal Code:47148-71167

Tel/Fax: +98-11-32339214



Website for the members of Computer Group:


B.Sc.: 1996-2000, Computer Hardware Engineering, University of Tehran, Tehran, Iran

M.Sc.: 2000-2003, Computer Engineering, Computer Architecture, University of Tehran, Tehran, Iran

Ph.D.: 2005-2010, Computer Engineering, Computer Architecture, University of Tehran, Tehran, Iran

Research Interests

§   Fault-Tolerant System Design, Reliability

§   Network-on-Chip (NoC) and Multi-Processor System-on-Chip (MP-SoC) Design

§   Computer Arithmetic

§ Reversible Logic

§   Computer Architecture

§   VLSI Architectures

Honors and Awards
Previous and Present Positions
  • Assistant professor of computer department since Oct. 2010
  • Head of computer department since Oct. 2011
Professional Membership

- IEEE Member since 2008

IEEE Computer Society Member since 2009

Reviewer of the following ISI-indexed publications:

  • IEEE Transactions of Reliability
  • Journal of Parallel and Distributed Computing (Elsevier)
  • Microelectronics Journal (Elsevier)
  • Computers and Electrical Engineering (Elsevier)
  • Journal of Systems Architecture (Embedded Software Design) (Elsevier)
  • IET Computers & Digital Techniques
  • Journal of Supercomputing (Springer)
  • Journa of Signal Processing Systems (Springer)
  • The Scientific World Journal (Hindawi)
  • International Journal of Communication Systems (IJCS)
  • Journal of Circuits, Systems and Computers (JCSC)
Reviewer of the following ISC-indexed publications:

  • International Journal of Engineering (IJE)
  • Electronics Industries Quarterly (EIQ)
  • Soft Computing and IT (JSCIT)
Reviewer of the other international publications:
  • International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS)
  • International Journal of High Performance Systems Architecture (IJHPSA)

Teaching Experiences


  • Digital Logic Circuits
  • Computer Architecture
  • Microprocessor
  • Computer Systems Architecture


  • Advanced Computer Architecture
  • Digital Circuit Design with VHDL
  • Fault-Tolerant System Design
  • Computer Arithmetic
  • Hardware Modeling and Design Methods

ISI-indexed Journal Papers: 

7- M. Valinataj and M. Shahiri, A low-cost, fault-tolerant and high-performance router architecture for on-chip networks,” Microprocessors and Microsystems, Elsevier, vol. 45, Part A, pp. 151-163, Aug. 2016.

6- M. Valinataj, M. Mirshekar, and H. Jazayeri, Novel low-cost and fault-tolerant reversible logic adders,Computers and Electrical Engineering, Elsevier, vol. 53, pp. 56-72, Jul. 2016.

5- M. ValinatajFault-tolerant carry look-ahead adder architectures robust to multiple simultaneous errors,” 

    Microelectronics ReliabilityElsevier, vol. 55, no. 12, Part B, pp. 2845-2857, Dec. 2015. 

4- M. ValinatajA novel self-checking carry lookahead adder with multiple error detection/correction,”Microprocessors and Microsystems, Elsevier, vol. 38, no. 8, Part B, pp. 10721081, Nov. 2014. 

3- M. Valinataj, S. Mohammadi, J. Plosila, P. Liljeberg, and H. Tenhunen, A reconfigurable and adaptive routing method for fault-tolerant mesh-based networks-on-chip,” International Journal of Electronics and Communications, Elsevier, vol. 65, no. 7, pp. 630–640, Jul. 2011.

2- M. Valinataj, S. Mohammadi, and S. Safari, Fault-aware and reconfigurable routing algorithms for networks-on-chip,” IETE Journal of Research, vol. 57, no. 3, pp. 215–223, May-Jun. 2011.

1- M. Valinataj, S. Mohammadi, and S.SafariReliability assessment of networks-on-chip based on analytical models,” Journal of Zhejiang University SCIENCE A, Springer, vol. 10, no. 12, pp. 18011814, Dec. 2009.

ISC-indexed Journal Papers:

4- F. Eslami Chalandar, M. Valinataj, and H. Jazayeri, Design of Error Detecting Serial Multipliers in Reversible Logic,” Electronics Industries Quarterly (EIQ), In Press (In Persian).

3- M. Taghizadeh Firoozjaee, M. Valinataj, and M. Mansoori, A Fault-Tolerant Routing Algorithm for 3D Networks-on-Chip,” Iranian Journal of Electrical and Computer Engineering (IJECE), vol. 14, no. 2, pp. 163-169, 2016 (In Persian).

2- M. Mirshekar, M. Valinataj, and H. Jazayeri, Design of Fault-Tolerant BCD Adders in Reversible Logic,” Electronics Industries Quarterly (EIQ), vol. 6, no. 4, pp. 51-62, 2015 (In Persian).

1- M. Valinataj“Reliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures,” International Journal of Engineering (IJE) Transactions A: Basics, vol. 27, no. 4, pp. 509–516, Apr. 2014.

International Conference Papers: 

11- M. Shahiri, M. Valinataj, and A. M. Rahmani, A Reliable and High-Performance Network-on-Chip Router Through Decoupled Resource Sharing,” Proc. of the 14th IEEE Intl. Conf. on High Performance Computing and Simulation (HPCS), pp. 88–95, Innsbruck, Austria, Jul. 2016.

10- M. Valinataj, P. Liljeberg, and J. Plosila, “Enhanced Fault-Tolerant Network-on-Chip Architecture Using Hierarchical Agents,” Proc. of the 16th IEEE Intl. Symp. on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 141–146, Karlovy Vary, Czech Republic, Apr. 2013.

9- M. Valinataj, P. Liljeberg, and J. Plosila, “Reliable On-Chip Network Design Using an Agent-based Management Method,” Proc. of the 19th Intl. Conf. on Mixed Design of Integrated Circuits and Systems (MIXDES), pp. 447–451, Warsaw, Poland, May 2012.

8- M. Valinataj, P. Liljeberg, and J. Plosila, “A Fault-Tolerant and Hierarchical Routing Algorithm for NoC Architectures,” Proc. of the 29th NORCHIP Conf., pp. 1–6, Lund, Sweden, Nov. 2011.

7- M. Valinataj, “Evaluation of Fault-Tolerant Routing Methods for NoC Architectures,” Proc. of the 14th EUROMICRO Conf. on Digital System Design, Architectures, Methods and Tools (DSD), pp. 446–449, Oulu, Finland, Aug.-Sep. 2011.

6- M. Valinataj and S. Mohammadi, “A Fault Aware, Reconfigurable and Adaptive Routing Algorithm for NoC Applications,” Proc. of the 18th IEEE/IFIP Intl. Conf. on VLSI and System-on-Chip (VLSI-SoC), pp. 13–18,MadridSpain, Sep. 2010.

5- M. Valinataj, S. Mohammadi, J. Plosila, and P. Liljeberg, “A Fault-Tolerant and Congestion Aware Routing Algorithm for Networks-on-Chip,” Proc. of the 13th IEEE Intl. Symp. on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 139144, Vienna, Austria, Apr. 2010.

4- M. Valinataj, S. Mohammadi, S. Safari, and J. Plosila, “A Link Failure Aware Routing Algorithm for Networks-on-Chip in Nano Technologies”, Proc. of the 9th IEEE Conf. on Nanotechnology (IEEE NANO), pp. 841844, Genoa, Italy, Jul. 2009.

3- M. Valinataj, S. Mohammadi and S. Safari, “Inherent Reliability Evaluation of Networks-on-Chip Based on Analytical Models,” Proc. of the 10th Intl. Symp. on System-on-Chip (ISSOC), pp. 98101, TampereFinland, Nov. 2008.

2- M. Valinataj and S. Safari, “Fault Tolerant Arithmetic Operations with Multiple Error Detection and Correction,”Proc. of the 22th IEEE Intl. Symp. on Defect and Fault-Tolerance in VLSI Systems (DFT), pp. 188–196Rome,Italy, Sep. 2007.

1- M. Valinataj and B. Foruzandeh, “Techniques to Reduce the Computational Complexity of G.729 Speech Coder,”Proc. of the 9th National Conf. on Communications (NCC), pp. 6569, India, Jan.-Feb. 2003.

Book chapters:

Mojtaba ValinatajTowards Reliability Assessment of On-Chip Networks using Analytical Models”, pp. 151174,

in book:  Networks – Emerging Topics in Computer ScienceCreateSpace Independent Publishing Platform, Mar. 2013.

Supervised Dissertations and Theses
Research Projects
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